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    <p>According to <a href="http://john.freml.in/amd64-nopl" rel="nofollow noreferrer">John Fremlin's blog: Operands to NOP on AMD64</a>, <code>nopw</code>, <code>nopl</code> etc. are <code>gas</code> syntax, not AT&amp;T syntax.</p> <p>Below are instruction encodings generated by <code>gas</code> for different <code>nop</code>'s from <a href="https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=gas/config/tc-i386.c;hb=binutils-2_30#l1211" rel="nofollow noreferrer"><code>gas</code> source</a> for instruction lengths from 3 to 15 bytes. Note that some are the same as Intel's recommended <code>nop</code> forms (see below), but not all. In particular, in longer <code>nop</code>'s <code>gas</code> uses multiple (up to 5) consecutive <code>0x66</code> operand prefixes in different <code>nop</code> forms, whereas Intel's recommended <code>nop</code> forms never use more than one <code>0x66</code> operand prefix in any single recommended <code>nop</code> instruction.</p> <p><code>nop</code> encodings from the <a href="https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob;f=gas/config/tc-i386.c;hb=binutils-2_30#l1211" rel="nofollow noreferrer">source code</a> for <strong>gas</strong> 2.30 (reformatted for readability):</p> <pre class="lang-c prettyprint-override"><code>/* nopl (%[re]ax) */ static const unsigned char alt_3[] = {0x0f,0x1f,0x00}; /* nopl 0(%[re]ax) */ static const unsigned char alt_4[] = {0x0f,0x1f,0x40,0x00}; /* nopl 0(%[re]ax,%[re]ax,1) */ static const unsigned char alt_5[] = {0x0f,0x1f,0x44,0x00,0x00}; /* nopw 0(%[re]ax,%[re]ax,1) */ static const unsigned char alt_6[] = {0x66,0x0f,0x1f,0x44,0x00,0x00}; /* nopl 0L(%[re]ax) */ static const unsigned char alt_7[] = {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; /* nopl 0L(%[re]ax,%[re]ax,1) */ static const unsigned char alt_8[] = {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; /* nopw 0L(%[re]ax,%[re]ax,1) */ static const unsigned char alt_9[] = {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ static const unsigned char alt_10[] = {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; static const unsigned char *const alt_patt[] = { f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, alt_9, alt_10 }; </code></pre> <p>Intel uses different syntax, and there are <code>nop</code>'s available for all instruction lengths from 1 to 9 bytes. There are several different <code>nop</code>'s, as all <code>nop</code>'s longer than two bytes accept 1 operand. One-byte <code>nop</code> (<code>0x90</code>) is synonymous with <code>xchg (e)ax,(e)ax</code>.</p> <p><a href="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html" rel="nofollow noreferrer">Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2 (2A, 2B &amp; 2C): Instruction Set Reference, A-Z, CHAPTER 4: INSTRUCTION SET REFERENCE, M-Z</a> lists recommended <code>nop</code> forms for different instructions lengths:</p> <pre><code>Table 4-12. Recommended Multi-Byte Sequence of NOP Instruction Length Assembly Byte Sequence 2 bytes 66 NOP 66 90H 3 bytes NOP DWORD ptr [EAX] 0F 1F 00H 4 bytes NOP DWORD ptr [EAX + 00H] 0F 1F 40 00H 5 bytes NOP DWORD ptr [EAX + EAX*1 + 00H] 0F 1F 44 00 00H 6 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00H] 66 0F 1F 44 00 00H 7 bytes NOP DWORD ptr [EAX + 00000000H] 0F 1F 80 00 00 00 00H 8 bytes NOP DWORD ptr [EAX + EAX*1 + 00000000H] 0F 1F 84 00 00 00 00 00H 9 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00000000H] 66 0F 1F 84 00 00 00 00 00H </code></pre> <p>So in addition to these <code>nop</code>'s recommended by Intel, there are many other <code>nop</code>'s too. In addition to aligning an instruction to a specific memory boundary, as Marc B mentions in his answer, <code>nop</code>'s are also very useful in self-modifying code, debugging and reverse-engineering.</p>
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