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    <p>Is your application multi-threaded? I read this a little while ago, maybe it doesn't apply for your situation, but very interesting nonetheless.</p> <p>Basically, the processor type combined with amount of cores and the memory model of your application can have a lot to say.</p> <p><a href="http://igoro.com/archive/volatile-keyword-in-c-memory-model-explained/" rel="nofollow">http://igoro.com/archive/volatile-keyword-in-c-memory-model-explained/</a></p> <p>Excerpt:</p> <blockquote> <p>On some processors, not only must the compiler avoid certain optimizations on volatile reads and writes, it also has to use special instructions. On a multi-core machine, different cores have different caches. The processors may not bother to keep those caches coherent by default, and special instructions may be needed to flush and refresh the caches.</p> <p>The mainstream x86 and x64 processors implement a strong memory model where memory access is effectively volatile. So, a volatile field forces the compiler to avoid some high-level optimizations like hoisting a read out of a loop, but otherwise results in the same assembly code as a non-volatile read.</p> <p>The Itanium processor implements a weaker memory model. To target Itanium, the JIT compiler has to use special instructions for volatile memory accesses: LD.ACQ and ST.REL, instead of LD and ST. Instruction LD.ACQ effectively says, “refresh my cache and then read a value” and ST.REL says, “write a value to my cache and then flush the cache to main memory”. LD and ST on the other hand may just access the processor’s cache, which is not visible to other processors.</p> </blockquote>
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