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    <blockquote> <p>Are threads grouped into Warps necessarily in order, 1 - 32, 33 - 64 ...?</p> </blockquote> <p>Yes, the programming model guarantees that the threads are grouped into warps in that specific order.</p> <blockquote> <p>As a simple example of optimizing of the divergent code paths can be used the separation of all the threads in the block in groups of 32 threads? For example: switch (threadIdx.s/32) { case 0: /* 1 warp*/ break; case 1: /* 2 warp*/ break; /* Etc */ }</p> </blockquote> <p>Exactly :)</p> <blockquote> <p>How many bytes must be read at one time for single Warp: 4 bytes * 32 Threads, 8 bytes * 32 Threads or 16 bytes * 32 Threads? As far as I know, the one transaction to the global memory at one time receives 128 bytes.</p> </blockquote> <p>Yes, transactions to global memory are 128 bytes. So, if each thread reads a 32-bit word from consecutive addresses (they probably need to be 128-byte aligned as well), all the threads in the warp can be serviced with a single transaction (4 bytes * 32 threads = 128 bytes). If each thread reads more bytes, or if the the addresses are not consecutive, more transactions need to be issued (with separate transactions for each separate 128-byte line that is touched).</p> <p>This is described in the CUDA Programming Manual 4.2, section F.4.2, "Global Memory". There's also a blurb in there saying that the situation is different with data that is cached only in L2, as the L2 cache has 32-byte cache lines. I don't know how to arrange for data to be cached only in L2 or how many transactions one ends up with.</p>
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    1. POWhy bother to know about CUDA Warps?
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    1. USRoger Dahl
    1. USRoger Dahl
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      1. VTUpMod
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    1. COThanks for the clarification. For data to be cached only in L2 need to use compiler option -Xptxas -dlcm=cg for nvcc. But i don't know where must i write (-Xptxas -dlcm=cg) in VS 2010 :)
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    2. COAnd if you can tell about the atomic operations and Warps. Which is better, the atomic's competition (concurrency) between threads of the single Warp or between threads of different Warps in one block? I think that when you access the shared memory is better when threads of one warp are competing with each other is less than the threads of different warps. And with access to global memory on the contrary, it is better that a threads of different warps of one block competed less than the threads of single warp, isn't it?
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