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    <p>All -</p> <p>A few corrections and updates. Section 5.6.6 of the 2001 Verilog Standard does not say that "unidirectional ports are just like continuous assignments," it says "Ports connect processes through implicit continuous assignment statements." There is a difference that I will note below. </p> <p>Second, "a continuous assignment is just an always block sensitive to everything," is not true. Continuous assignments <strong><em>Drive</em></strong> values onto nets that can be driven by other sources with pre-defined resolution functions as described in the Verilog Standard. Always blocks <strong><em>Change</em></strong> values of variables and last procedural change wins (no resolution).</p> <p>Regarding my description of the 1-always block flip-flop, my description in the paper is not 100% accurate (but is usually accurate). The 2-instantiated flip-flop model in theory does have a race condition, though it is rarely seen. The race is rarely seen because when you make an always block assignment to a variable that is declared as an output, Verilog compilers automatically throw in an "implicit continuous assignment statement" (IEEE-1364-2001, Section 5.6.6, 1st paragraph) to convert the procedural variable into a net-<strong><em>Driving</em></strong> assignment (you never see this happen!) This conversion is typically sufficient to introduce the equivalent of a nonblocking assignment delay on the port, so the simulation works. I have experimented in the past with compiler optimization switches that effectively remove the module ports between the flip-flops and have observed the unwanted race conditions, so technically, my description of an okay 1-always, blocking-assignment flip-flop is not 100% correct; hence, you should still use the nonblocking assignments described in the paper. </p> <p>The 2-always blocking-assignment example in the same module has a definite race condition. As written, it will probably work because most compilers execute the code top-down, but if you reverse the order of the always blocks, you will probably see a race.</p> <p>Regards - Cliff Cummings - Verilog &amp; SystemVerilog Guru</p>
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    1. COMany thanks for the answer.
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