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POUsing blocking assignments to infer flip-flops in Verilog
 

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  1. POUsing blocking assignments to infer flip-flops in Verilog
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    <p>I have read "Nonblocking Assignments in Verilog Synthesis, Coding Styles that Kill!" by Clifford Cummings. He says that the following code (page 12, simplified) is a correct implementation of a flip-flop often used in textbooks, even if not exactly the kind that anyone should use. The <a href="http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf" rel="nofollow">document</a> won a best paper award, so I assume the claim is true.</p> <pre><code>module ff (q, d, clk) output q; input d, clk; reg q; always @(posedge clk) q = d; endmodule </code></pre> <p>I would like to know why this would continue to work correctly if two or more of these flip-flops were connected in series. Say </p> <pre><code>module two_ffs (q, d, clk) input d, clk; output q; wire tmp; ff firstff (tmp, d, clk); ff secondff (q, tmp, clk); endmodule </code></pre> <p>The way I see it, it's possible that the value of tmp is updated before it is used by secondff, thus resulting in one flip-flop rather than two. Can someone please tell me what part of the standard says that cannot happen? Many thanks.</p> <p><em>[not that I would ever contemplate writing code like that, I just want to understand the blocking/nonblocking behavior even in cases when poor coding style makes the meaning non-obvious]</em></p> <p>Added later:</p> <p>I now think the paper is unlikely to be correct. Section 5 "Scheduling Semantics" of the 1364-2201 Verilog standard explains what happens. In particular, section 5.6.6 "Port connections" on page 68 says that unidirectional ports are just like continuous assignments. In turn, a continuous assignment is just an always block sensitive to everything. So the bottom line is that that the two instantiations of an ff in my example below are equivalent to a module with multiple always clauses, which everyone would agree is broken.</p> <p>Added after Clive Cummings answered the question:</p> <p>I am grateful to CC for pointing out that that the statements above taken out of section 5 of the standard only refer to the timing of update events, and do not imply literal equivalence between e.g. some continuous assignments and always blocks. Nevertheless, I think they explain why some simulators (e.g. Icarus Verilog) will produce different simulation results with a blocking and a non-blocking assignment in the "flip-flop". [On a larger example, I got 2 apparent ffs with a blocking assignment, and the correct five with a non-blocking one.] Other simulators (e.g. Modelsim with default options or Cver) seem to produce the same result no matter which form of assignment is used.</p>
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    1. COAre you sure that this is an example of a **correct** implementation? That looks like a textbook example of an incorrect design to me. I think your understanding is correct.
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    2. COI actually don't see that first section anywhere in [this paper](http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf) . I think you're probably misreading it, or can you point to exactly where you got that code sample from? I don't see it on page 12 (I may have a different version than you).
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    3. COTim: sorry about not providing a link (added now). I refer to rev 1.3 of the document whereas you found rev 1.2. Sorry again. It is in section 9 in both documents. "Example 13 shows a flipflop model that appears in most Verilog test books". Then its caption is "Simple flawed ..... but it works!".
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