Databases
StackOverflow2013
Postsdbo
POif elsif vhdl behavior
 

Note that there are some explanatory texts on larger screens.

plurals
  1. POif elsif vhdl behavior
    primarykey
    data
    text
    <p>I am using webPack ISE v 13 to program a Nexys 3 board with the following piece of code and notice completely different behavior by swapping statements in the if elsif statement. In essence, I'm using three pushbuttons on the board: when pressing the first pushbutton btn(0), the state of 8 switches is stored in a register. When I press btn(1), the state of the switches should be displayed in the 8 leds and the leds should keep this state. When I press btn(2), I force all leds to be lit and they should stay this way if neither btn 1 or 2 is pressed. By swapping the actions under the if and elsif for buttons 1 &amp; 2, the behavior changes: the state of the switches is only displayed when I press the corresponding button and once I let go, all LEDs light up. </p> <p>More than looking for a "this is what you need to make it work", I'm after an explanation of why vhdl behaves so differently from C++ let's say (in this instance where the order wouldn't matter)</p> <p>Below is the code excerpt; I indicate which lines to comment/uncomment to get behavior 'a' or behavior 'b'.</p> <h3>Behavior 'a':</h3> <ul> <li>when pressing btn(0) the state of the 8 switches loads correctly into the data_reg </li> <li>when I press the btn(1), the LEDs are all ON ("111...11") </li> <li>if I press btn(2), the LEDs display the data_reg contents </li> <li>If no button is pressed, the state of the LEDs is that commanded by the last button press</li> </ul> <h3>Behavior 'b':</h3> <ul> <li>when pressing btn(0) the state of the 8 switches loads correctly into the data_reg</li> <li>when I press btn(1), the LEDs display the data_reg contents </li> <li>if I press btn(2), the LEDs are all ON ("111...11") </li> <li>If no button is pressed, all LEDs are ON &amp; the only way to see the contents of the data_reg is to hold btn(1) depressed.</li> </ul> <p>`</p> <blockquote> <p>process(clk)</p> <blockquote> <p>begin</p> <blockquote> <pre><code>if (clk'event and clk='1') then </code></pre> <blockquote> <pre><code> if (db_btn(0)='1') then --load sw state into data_reg data_reg &lt;= sw; end if; </code></pre> <p>end if; end process;</p> </blockquote> </blockquote> </blockquote> </blockquote> <pre><code> process(btn,data_reg) begin if btn(1)='1' then data_s2f &lt;= "1111111111111111"; --behvr a; comment this line for behvr b -- data_s2f &lt;= "00000000" &amp; data_reg; -- uncomment for behvr b; comment for behvr a elsif btn(2)='1' then -- read data_s2f &lt;= "00000000" &amp; data_reg; --behvr a; comment this line for behvr b --data_s2f &lt;= "1111111111111111"; -- uncomment for behvr b; comment for behvr a end if; end process; -- output led &lt;= data_s2f(7 downto 0); --display data_s2f in LEDs </code></pre> <hr> <h2>SIMULATION TESTBENCH</h2> <p>Here is my simulation testbench. Whenever I executed the result for all signals is UUU..UU Any comments would be greatly appreciated:</p> <pre><code>LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY ifstmt_tb IS END ifstmt_tb; ARCHITECTURE behavior OF ifstmt_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ram_ctrl_test PORT( clk : IN std_logic; reset : IN std_logic; sw : IN std_logic_vector(7 downto 0); btn : IN std_logic_vector(2 downto 0); led : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal sw : std_logic_vector(7 downto 0) := (others =&gt; '0'); signal btn : std_logic_vector(2 downto 0) := (others =&gt; '0'); --Outputs signal led : std_logic_vector(7 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ram_ctrl_test PORT MAP ( clk =&gt; clk, reset =&gt; reset, sw =&gt; sw, btn =&gt; btn, led =&gt; led ); -- Clock process definitions clk_process :process begin clk &lt;= '0'; wait for clk_period/2; clk &lt;= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. reset &lt;= '1'; sw &lt;= "11001100"; btn&lt;= (others =&gt; '0'); wait for 100 ns; reset &lt;= '0'; wait for clk_period*10; -- load register btn&lt;= (0=&gt;'1', others =&gt; '0'); wait for clk_period*2; btn&lt;= (others =&gt; '0'); wait for clk_period*10; -- display with btn 1 btn&lt;= (1=&gt;'1', others =&gt; '0'); wait for clk_period*5; btn&lt;= (others =&gt; '0'); wait for clk_period*10; -- display with btn 2 btn&lt;= (2=&gt;'1', others =&gt; '0'); wait for clk_period*5; btn&lt;= (others =&gt; '0'); wait for clk_period*10; -- change pattern sw &lt;= "11100111"; wait for clk_period; -- load register btn&lt;= (0=&gt;'1', others =&gt; '0'); wait for clk_period*2; btn&lt;= (others =&gt; '0'); wait for clk_period*10; -- display with btn 2 btn&lt;= (2=&gt;'1', others =&gt; '0'); wait for clk_period*5; btn&lt;= (others =&gt; '0'); wait for clk_period*10; -- display with btn 1 btn&lt;= (1=&gt;'1', others =&gt; '0'); wait for clk_period*5; btn&lt;= (others =&gt; '0'); -- insert stimulus here wait; end process; END; </code></pre>
    singulars
    1. PO
      singulars
      1. PTAnswer
    1. This table or related slice is empty.
    1. PTQuestion
    1. USirobot
    1. USirobot
    plurals
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. PO
      singulars
      1. PTAnswer
    2. PO
      singulars
      1. PTAnswer
    3. PO
      singulars
      1. PTAnswer
    1. VO
      singulars
      1. POif elsif vhdl behavior
      1. This table or related slice is empty.
      1. VTUpMod
    2. VO
      singulars
      1. POif elsif vhdl behavior
      1. This table or related slice is empty.
      1. VTUpMod
    1. COHow are `db_btn` and `btn` connected?
      singulars
      1. POif elsif vhdl behavior
      1. USbmk
    2. COWhat does your simulator say?
      singulars
      1. POif elsif vhdl behavior
      1. USsimon
    3. CObmk: btn is the input to a debounce component whose output is db_btn.
      singulars
      1. POif elsif vhdl behavior
      1. USirobot
 

Querying!

 
Guidance
A row detail

Detail views are divided into sections. All the information in the data section comes from columns in the selected row. The other sections display data from other, related rows.

Related data can be related in a to-one or a to-many fashion. Captions of data related in a to-many fashion link to a list view showing a filtered view of the table.

Try moving around until you find a non-empty to-many entry and click on the label to get to one. You can move back to the root by clicking on the database name in the header.

SQuiL has stopped working due to an internal error.

If you are curious you may find further information in the browser console, which is accessible through the devtools (F12).

Reload