Databases
StackOverflow2013
Postsdbo
PO
 

Note that there are some explanatory texts on larger screens.

plurals
  1. PO
    primarykey
    data
    text
    <p>Try using EMON profiling in Vtune, or some equivalent tool like oprof</p> <ul> <li><a href="http://software.intel.com/en-us/articles/intel-vtune-performance-analyzer-for-linux-installation-limitations-for-vtune-analyzer-90-for-linux/" rel="nofollow">Vtune for Linux</a> (you can search for the Windows version)</li> <li><a href="http://oprofile.sourceforge.net/about/" rel="nofollow">oprofile</a></li> </ul> <p>EMON (Event Monitoring) profiling => like a time based tool, but it can tell you what performance event is causing the problem. Although, you should start out with a time based profile first, to see if there is a particular instruction that jumps out. (And possibly the related events that tell you how often there was a retirement stall at that IP.)</p> <p>To use EMON profiling, you must run through a list of events, ranging from "the usual suspects" to ... </p> <p>Here, I would start off with cache misses, alignment. I do not know if the processor you are using has a counter for RF port limitations - it should - but I added EMON profiling long ago, and I don't know how well they are keeping up by adding events appropriate for microarchitecture.</p> <p>It may also be possible that it is a front end, instruction fetch, stall. How many bytes are in these instructions, anyway? There are EMON events for that, too.</p> <hr> <p>Responding to comment that Nehalem VTune can't see L3 events: not true. Here is stuff I was adding to comment, but did not fit:</p> <p>Actually, there ARE performance counters for the LL3 / L3$ / so-called Uncore. I would be immensely surprised if VTune doesn't support them. See <a href="http://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf" rel="nofollow">http://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf</a> points to VTune and other tools such as PTU. In fact, even without LL3 events, as David Levinthal says: "the Intel® Core™ i7 processor has a “latency event” which is very similar to the Itanium® Processor Family Data EAR event. This event samples loads, recording the number of cycles between the execution of the instruction and actual deliver of the data. If the measured latency is larger than the minimum latency programmed into MSR 0x3f6, bits 15:0, then the counter is incremented. Counter overflow arms the PEBS mechanism and on the next event satisfying the latency threshold, the measured latency, the virtual or linear address and the data source are copied into 3 additional registers in the PEBS buffer. Because the virtual address is captured into a known location, the sampling driver could also execute a virtual to physical translation and capture the physical address. The physical address identifies the NUMA home location and in principle allows an analysis of the details of the cache occupancies." He also points, on page 35, to VTune events such as L3 CACHE_HIT_UNCORE_HIT and L3 CACHE_MISS_REMOTE_DRAM. Sometimes you need to look up the numeric codes and program them into VTune's lower level interface, but I think in this case it is visible in the pretty user interface.</p> <hr> <p>OK, in <a href="http://software.intel.com/en-us/forums/showthread.php?t=77700&amp;o=d&amp;s=lr" rel="nofollow">http://software.intel.com/en-us/forums/showthread.php?t=77700&amp;o=d&amp;s=lr</a> a VTune programmer in Russia (I think) "explains" that you can't sample on Uncore events. </p> <p>He's wrong - you could, for example, enable only one CPU, and sample meaningfully. I also believe that there is the ability to mark L3 missing data as it returns to the CPU. In fact, overall the L3 knows which CPU it is returning data to, so you can definitely sample. You may not know which hyperthread, but again you can disable, go into single thread mode.</p> <p>But it looks like, as is rather common, you would have to work AROUND VTune, not with it, to do this. </p> <p>Try latency profiling first. That's entirely inside the CPU, and the VTune folks are unlikely to have messed it up too much.</p> <p>And, I say again, likelihood is that your problem is in the core, not in L3. So VTune should bne able to handle that.</p> <hr> <p>Try "Cycle Accounting" per Levinthal.</p>
    singulars
    1. This table or related slice is empty.
    1. POC code loop performance [continued]
      singulars
      1. PTQuestion
    1. PTAnswer
    1. This table or related slice is empty.
    1. USKrazy Glew
    plurals
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. This table or related slice is empty.
    1. VO
      singulars
      1. PO
      1. This table or related slice is empty.
      1. VTUpMod
    2. VO
      singulars
      1. PO
      1. This table or related slice is empty.
      1. VTUpMod
    3. VO
      singulars
      1. PO
      1. This table or related slice is empty.
      1. VTUpMod
    1. COThanks for your reaction. I use VTune to analyze my application, but the problem with the nehalem architecture is that the L3 cache belongs to the `off-core` part of the core, so there are no performance event counters available for this part. Therefore it is hard to estimate cache misses etcetera.
      singulars
      1. PO
      1. USRicky
    2. COActually, there ARE performance counters for the LL3 / L3$ / so-called Uncore. I would be immensely surprised if VTune doesn't support them. See http://software.intel.com/sites/products/collateral/hpc/vtune/performance_analysis_guide.pdf
      singulars
      1. PO
      1. USKrazy Glew
    3. COI wrote more than would fit in comment, tried to move it to the answer and clean up the original comment, but comments can only bwe edited for 5 minutes. Short version: VTune allows you to see L3 cache misses. Even without Uncore support, using latency profiling - and it has Uncore support.
      singulars
      1. PO
      1. USKrazy Glew
 

Querying!

 
Guidance
A row detail

Detail views are divided into sections. All the information in the data section comes from columns in the selected row. The other sections display data from other, related rows.

Related data can be related in a to-one or a to-many fashion. Captions of data related in a to-many fashion link to a list view showing a filtered view of the table.

Try moving around until you find a non-empty to-many entry and click on the label to get to one. You can move back to the root by clicking on the database name in the header.

SQuiL has stopped working due to an internal error.

If you are curious you may find further information in the browser console, which is accessible through the devtools (F12).

Reload