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POUsing a make file to compile files in separate directories
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2012-04-06T13:50:50.263
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2012-04-07T21:32:39.220
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OK, I have never been able to grasp make, and makefiles. I've tried reading through the manpages with no luck. So I have come here :L I have a bunch of files that are starting to get very un-managed in one file. ( I'm trying to make an OS ) And I want to try and split these files into separate sub-directories ( see structure below ) and then tell make to 'make' the files into an their .o files, moving them into another separate sub-directory and finally ending up with a kernel file. ( Sorry if that sounds complicated, hopefully the structure will help make things clearer ) So this is my intended structure tree: <pre><code> Parent directory ( where the makefile will be ) | | ------------------------------------------------------------------------- | | | | | Header SubDir Source SubDir ASM SubDir Obj SubDir Kern SubDir (Header files ) (Source Files) (Assembly Files) (Object Files) (Kernel File) </code></pre> This is my current makefile: <pre><code>C_SOURCES= main.c S_SOURCES= boot.s C_OBJECTS=$(patsubst %.c, obj/%.o, $(C_SOURCES)) S_OBJECTS=$(patsubst %.s, obj/%.o, $(S_SOURCES)) CFLAGS=-nostdlib -nostdinc -fno-builtin -fno-stack-protector -m32 -Iheaders LDFLAGS=-Tlink.ld -melf_i386 --oformat=elf32-i386 ASFLAGS=-felf all: kern/kernel .PHONY: clean clean: -rm -f kern/kernel kern/kernel: $(S_OBJECTS) $(C_OBJECTS) ld $(LDFLAGS) -o $@ $^ $(C_OBJECTS): obj/%.o : %.c gcc $(CFLAGS) $< vpath %.c source $(S_OBJECTS): obj/%.o : %.s nasm $(ASFLAGS) $< vpath %.s asem </code></pre> It's now spitting out this error: <pre><code>ld -Tlink.ld -melf_i386 --oformat=elf32-i386 -o kern/kernel obj/boot.o obj/main.o ld: cannot find obj/boot.o: No such file or directory ld: cannot find obj/main.o: No such file or directory </code></pre> Thanks for any help in advance! Jamie. 
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Using a make file to compile files in separate directories
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