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POverilog always, begin and end evaluation
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  1. POverilog always, begin and end evaluation
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    copied!<p>I'm trying to learn Verilog using Pong P. Chu's book. I have a question about how an always block is evaluated and implemented. A style in the authors code is confusing me. </p> <p>In this example he codes an FSM with two output registers 'y1' and 'y2'. The part I'm confused about is in the NEXT STATE LOGIC AND OUTPUT LOGIC always block, where after the begin statement and <code>always@*</code> y1 and y0 are set to 0. I seems that regardless of state, y1 and y0 will toggle to 0 on every clock cycle and signal change. According to state diagram in the book reg y1 should be equal to 1 while in state 0 or 1. </p> <p>So does y1 toggle to 0 every clock cycle then back to what ever its value at the present state?? I assume that's not the case and that I'm just confused about how the block is evaluated. Can someone explain what that part of the code is doing. I'm lost. Thanks</p> <pre><code>module fsm_eg_2_seg ( input wire clk, reset, a, b, output reg y0, y1 ); //STATE DECLARATION localparam [1:0] s0 =2'b00, s1=2'b01, s2=2'b10; // SIGNAL DECLARATION reg [1:0] state_reg, state_next ; //STATE REGISTER always @(posedge clk, posedge reset) if (reset) state_reg &lt;= s0; else state_reg &lt;= state_next; //NEXT STATE LOGIC AND OUTPUT LOGIC always @* begin state_next = state_reg; // default next state: the same y1 = 1'b0; // default output: 0 y0 = 1'b0; // default output: 0 case (state_reg) s0: begin y1 = 1'b1; if (a) if(b) begin state_next = s2; y0 = 1'b1; end else state_next = s1; end s1: begin y1 = 1'b1; if (a) state_next = s0; end s2: state_next = s0; default: state_next = s0; endcase end endmodule </code></pre>
 

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