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POsynopsys tetramax strange error in parcing vectors from VCD
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  1. POsynopsys tetramax strange error in parcing vectors from VCD
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    copied!<p>I am a Tetramax Newby and i am trying to get a mesure of fault coverage loading functional test vector generated by modelsim. I generate the modelsim test vector following this procedure:</p> <pre><code>vsim work.TbTop view wave wave create -pattern none -portmode out -language vhdl -range 15 0 //tbtop/outport restart TbTop.vhd vcd dumpports -file alwcpuSimDump.vcd /TbTop/alwcpu66/* run 1000 quit -sim </code></pre> <p>and i later load such a VCD in tetramax with the following command</p> <pre><code>set patterns external ./externalFaults/alwcpuSimDump.vcd -insensitive -strobe rising clock -strobe offset 180 ns </code></pre> <p>First error appearing was the fact that signals where capital and lower case in different files (solved by using -insensitive). Second problem is that std_logic_vector are not recognised while parcing the VCD.</p> <p>This is the error I get: </p> <blockquote> <p>missing definition (No such port "adr_o[15]"). (V4-1)</p> </blockquote> <p>but in the VCD the port is present as shown here:</p> <pre><code>$var port 1 &lt;0 clk_i $end $var port 1 &lt;1 rst_i $end $var port 1 &lt;2 cyc_o $end $var port 1 &lt;3 stb_o $end $var port 1 &lt;4 sel_o $end $var port 1 &lt;5 we_o $end $var port 1 &lt;6 ack_i $end $var port [15:0] &lt;7 adr_o $end $var port [15:0] &lt;8 dat_o $end $var port [15:0] &lt;9 dat_i $end </code></pre> <p>as well as it is present in the netlist as shown here:</p> <pre><code>entity cpu is port( CLK_I, RST_I : in std_logic; CYC_O, STB_O, SEL_O, WE_O : out std_logic; ACK_I : in std_logic; ADR_O, DAT_O : out std_logic_vector (15 downto 0); DAT_I : in std_logic_vector (15 downto 0)); end cpu; </code></pre> <p>did anyone experienced such a problem? Any idea about why this happens or how to fix it??</p> <p>Cheers,</p>
 

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