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copied!<p>Generally speaking, GNU make doesn't support targets with multiple outputs. However, there is an exception to that rule: pattern rules. If you can structure your makefile such that it uses pattern rules to generate the object files, you may be able to achieve your goals. For example:</p> <pre><code>.DELETE_ON_ERROR: all: foo.o %.o %.d: %.c @touch $*.d @touch $*.o @exit 1 </code></pre> <p>You'll see that with this makefile when the "error" is detected in the rule, both the .d and the .o file are deleted. The advantage to this approach is that it more accurately expresses the dependency graph by describing how the .d file is to be generated and what rule will produce it.</p> <p>Alternatively, a common paradigm in this case is just as you suggested: have GCC generate the .d file into a temporary file name and only move it into place after the GCC command has completed successfully. Usually this is accomplished with a trick of the shell:</p> <pre><code>all: foo.o %.o: %.c gcc -o $@ -MMD -MF $(basename $@).d.tmp -c $< \ && mv $(basename $@).d.tmp $(basename $@).d </code></pre> <p>Here the "magic" trick is the use of the GCC flags <code>-MMD</code>, which generates the dependency file as a side-effect of compilation, and <code>-MF</code>, which lets you specify the output name for the dependency file; and the use of the shell <code>cmd1 && cmd2</code> syntax, which causes the shell to only execute <code>cmd2</code> if <code>cmd1</code> exits successfully.</p>

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