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copied!<p>You'd need to learn about Virtual Memory first, but basically it's this:</p> <ul> <li><p>The memory addresses your program uses aren't the <em>physical</em> addresses that the RAM uses; they're <em>virtual</em> addresses <em>mapped</em> to physical addresses by the CPU.</p></li> <li><p>Multiple virtual addressses can point to the same physical address.</p></li> </ul> <p>That means that you can have two copies of the same data in separate parts of the cache without knowing it... and they wouldn't be updated correctly, so you'd get wrong results.</p> <hr> <h3>Edit:</h3> <p>Exerpt of <a href="ftp://download.nvidia.com/XFree86/Linux-x86_64/256.35/README/knownissues.html">reference</a>:</p> <blockquote> <p>Cache aliasing occurs when <em>multiple mappings to a physical page</em> of memory have conflicting caching states, such as cached and uncached. Due to these conflicting states, data in that physical page may become corrupted when the processor's cache is flushed. If that page is being used for DMA by a driver, this can lead to hardware stability problems and system lockups.</p> </blockquote> <hr> <p><a href="http://msdn.microsoft.com/en-us/library/bb905767.aspx">For those who are still unconvinced</a>:</p> <blockquote> <p>On ARMv4 and ARMv5 processors, cache is organized as a virtual-indexed, virtual-tagged (VIVT) cache in which both the index and the tag are based on the virtual address. The main advantage of this method is that cache lookups are faster because the translation look-aside buffer (TLB) is not involved in matching cache lines for a virtual address. However, this caching method does require more frequent cache flushing <em>because of cache aliasing, in which <strong>the same physical address can be mapped to multiple virtual addresses</em></strong>.</p> </blockquote>

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