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copied!<p>Think about what commands you would issue without <code>make</code>. What steps would you take? Which files do you create first, and how do files depend on the existence of others before they can be made?<br> Once you have a clear picture of that, write make rules that mimic those commands, but with the inclusion of make variables. </p> <p>If you have that down, you can then enhance your makefile by using things like implicit rules, automatic variables, and such, but keep it simple at first, until you get a grasp of how <code>make</code> works.</p> <p>A couple of points: </p> <ul> <li>I don't think the wildcard function will pick up any file names in this way. It only looks in the current directory, and doesn't use VPATH to search in others.</li> <li>You use gcc with the objects as inputs. This way it will (try to) create an executable.</li> <li>You have no rules to create the object files. This may be fine if you rely on <code>make</code>'s built-in implicit or pattern rules, but it won't use the version of gcc you want to use, with it's associated flags. You have to set up some other variables for that to work (like <code>CC</code>, <code>CFLAGS</code>, and such).</li> <li>You have defined <code>LD</code>, but never use it. Use it in a recipe to create the executable.</li> </ul> <p>I guess you should have something more like this:</p> <pre><code>all: $(EXE) $(EXE): $(OBJECTS_AS) $(OBJECTS_GCC) $(LD) $^ %.o: %.s $(AS) $< %.o: %.c $(GCC) -c $< </code></pre>

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