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POHow can I build variants of an executable with one makefile?
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  1. POHow can I build variants of an executable with one makefile?
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    copied!<p><br> I have one set of source files from which I need to generate multiple variants of an executable. For example I need to generate <strong>app1.elf</strong>, <strong>app2.elf</strong>, <strong>app3.elf</strong> from the same <strong>main.c</strong> and <strong>comm.c</strong>. The difference between each of the apps is a node address, a parameter that is passed down in the invocation of gcc. i.e.:</p> <pre><code>gcc -DNODE=1 -oapp1.elf main.c gcc -DNODE=2 -oapp2.elf main.c gcc -DNODE=3 -oapp3.elf main.c </code></pre> <p>Let's assume that I have the following files: </p> <ul> <li>src/main.c</li> <li>src/comm.c</li> </ul> <p>When I run the Makefile as so:</p> <blockquote> <p>make all_nodes</p> </blockquote> <p>make only builds app1.elf with the following output:</p> <blockquote> <p>Built app1<br> Built app2<br> Built app3 </p> </blockquote> <p><strong>FAIL!</strong> The output seems to suggest that it worked, however it only generates one executable, namely app1.elf. Anybody care to point out what I'm doing wrong? </p> <p>To further explain my Makefile, I've created a <em>cleanobjs</em> target to clean out the objects in the ./obj subdirectory. This is my attempt at having 'make' rebuild the obj files with the new <strong>node</strong> address, but it fails. Am I using 'make' in a way it wasn't intended to be used? I know I can also create a batch file to run make (something I've done sucessfully) but I'd like to know what I'm doing wrong. My Makefile is below:</p> <pre><code>obj/%.o: src/%.c gcc -DNODE=$(NODE) -o$@ $&lt; app.elf : ./obj/main.o ./obj/comm.o gcc -oapp$(NODE).elf main.o comm.o node1 : NODE=1 node1 : cleanobj app.elf @echo 'Built app1' node2 : NODE=2 node2 : cleanobj app.elf @echo 'Built app2' node3 : NODE=3 node3 : cleanobj app.elf @echo 'Built app3' all_nodes : node1 node2 node3 cleanobj : rm -rf obj/main.o obj/comm.o .PHONY : cleanobj </code></pre>
 

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