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copied!<p>How do you want the compiler to know if your std_logic_vectors are signed or unsigned ? Adder implementation is not the same in these two cases, so you need to explicitly tell the compiler what you want it to do ;-)</p> <p><em>Note: VHDL syntax highlighting in StackOverflow is crappy. Copy/paste this code in your preferred VHDL editor to read it more easily.</em></p> <pre><code>library IEEE; use IEEE.std_logic_1164.all; -- use IEEE.std_logic_arith.all; -- don't use this use IEEE.numeric_std.all; -- use that, it's a better coding guideline -- Also, never ever use IEEE.std_unsigned.all or IEEE.std_signed.all, these -- are the worst libraries ever. They automatically cast all your vectors -- to signed or unsigned. Talk about maintainability and strong typed language... entity add_module is port( pr_in1 : in std_logic_vector(31 downto 0); pr_in2 : in std_logic_vector(31 downto 0); pr_out : out std_logic_vector(31 downto 0) ); end add_module; architecture Behavior of add_module is begin -- Here, you first need to cast your input vectors to signed or unsigned -- (according to your needs). Then, you will be allowed to add them. -- The result will be a signed or unsigned vector, so you won't be able -- to assign it directly to your output vector. You first need to cast -- the result to std_logic_vector. -- This is the safest and best way to do a computation in VHDL. pr_out <= std_logic_vector(unsigned(pr_in1) + unsigned(pr_in2)); end architecture Behavior; </code></pre>

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