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  1. PO"Serialize" VHDL record
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    copied!<p>Suppose I have the following type definition which relies on constants to indicate vector length of the record members:</p> <pre><code>type point_t is record x: std_logic_vector(X_WIDTH-1 downto 0); y: std_logic_vector(Y_WIDTH-1 downto 0); end record; </code></pre> <p>I would like to convert these kind of records into <code>std_logic_vector</code>s to put them into, say, a FIFO. Currently I am using the following code:</p> <pre><code>PROCEDURE encodepoint(signal pnt: in point_t; signal d: out std_logic_vector(POINT_ENC_WIDTH-1 downto 0)) is variable top: integer := 0; begin top := X_WIDTH-1; d(top downto 0) &lt;= pnt.x; top := top + Y_WIDTH; d(top downto top-X_WIDTH+1) &lt;= sl.y; d(d'left downto top+1) &lt;= (others =&gt; '0'); end; </code></pre> <p>This code is suboptimal in many ways. For example it requires me to always correctly set POINT_ENC_WIDTH to a value that is big enough to allow <code>d</code> to hold the whole serialized record. It relies on the programmer to do very mechanical work. For example for every member of the record, say <code>x</code>, <code>X_WIDTH</code> appears <em>twice</em> in the code, once in direct connection with <code>x</code> and once in connection with the next member, <code>y</code>. This get tedious quickly. If I change the definition of the record by adding additional fields, I have to update both the serializing and the (very similar) deserializing code, and I may just forget this. When I remove fields, at least the compiler complains. </p> <p>Thus this leads me to my question: Is there a simple, automated or at least quasi-automated way to convert VHDL records into <code>std_logic_vector</code>s without having to resort to manually written serializing/unserializing code? It is not important for me to know the specific encoding, as I am using the records internally and the final output format is clearly specified and will be implemented manually.</p>
 

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