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POSimple State Machine Problem
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  1. POSimple State Machine Problem
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    copied!<p>I have a very simple FSM which should drive some output signals of an external RAM. The problem that I have comes with handling the data bus which can be input as well as output... I am not too sure how I can handle best this case in my FSM. The problem comes from the following line:</p> <pre><code> v.sram_data &lt;= io_sram_data; </code></pre> <p>Obviously, the left hand side is a variable while the right hand side is a signal. Is there a "nice" way how to handle inout signals in a FSM as the one I have?</p> <pre><code>entity sram_fsm is port ( clk : in std_logic; reset : in std_logic; out_sram_rd : out std_logic; out_sram_wr : out std_logic; out_sram_addr : out std_logic_vector(3 downto 0); io_sram_data : inout std_logic_vector(7 downto 0) ); end; architecture Behavioral of sram_fsm is type state_type is (wr_init, wr_data, rd_init, rd_data); type reg_type is record state : state_type; sram_data : std_logic_vector(7 downto 0); sram_addr : std_logic_vector(3 downto 0); sram_rd : std_logic; sram_wr : std_logic; end record; signal r, rin : reg_type; begin comb : process (r) variable v : reg_type; begin v := r; case r.state is when wr_init =&gt; v.sram_data := "00000000"; v.sram_addr := "0000"; v.sram_rd := '0'; v.sram_wr := '0'; v.state := wr_data; when wr_data =&gt; io_sram_data &lt;= "00001000"; v.sram_wr := '1'; v.state := rd_init; when rd_init =&gt; v.sram_addr := "0000"; v.sram_rd := '1'; v.sram_wr := '0'; v.state := wr_data; when rd_data =&gt; v.sram_data &lt;= io_sram_data; v.state := wr_init; end case; out_sram_addr &lt;= v.sram_addr; out_sram_rd &lt;= v.sram_rd; out_sram_wr &lt;= v.sram_wr; rin &lt;= v; end process; regs : process (reset, clk) begin if reset = '0' then r.state &lt;= wr_init; elsif rising_edge(clk) then r &lt;= rin; end if; end process; end Behavioral; </code></pre> <p>Many thanks for comments that code improve this simple FSM!</p>
 

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