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POGlobal Placement Phase 8.8 Running Indefinitely, Xilinx
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copied!<p>Once again my battle with Xilinx tools continues. I am running implementation for a design on the Zynq7020 in PlanAhead-14.7. The design uses roughly 15-20% device utilization on the PL, the implementation process seems to get stuck on Global Placement which so far has been running for over 12hrs (and still running), I was only expecting an hour max, and this is massively inconvenient as I need to have the design built and tested by Friday, which leaves me hanging dry given that any refinements will take another 12hr+ to place again! </p> <p>I am using the 64bit 14.7 design suite, and read that previous versions had a similar problem for the 64bit tools. Is there anything I can do to speed-up the global placement? And I've checked that all the placement flags have been set to give the fastest possible placement. </p> <p>--UPDATE 2-- I am now on the verge of insanity, as such this is the whole process (and design refinements mentioned by Brian) which is causing me grief, and it is something to do with the OR statements using the state = fwrd_init and state = bkwrd_init</p> <pre><code>input : process(clk, rst, dz_ready, row_ready, d_div_stts, counter, bkwrd_stts, state, cd_empty, zd_empty) begin if(clk'event and clk='1') then stack_en <='0'; bkwrd_drdy <= '0'; d_rdy <= '0'; dz_read <='0'; read_row <='0'; result_ready <='0'; --delay dz_ready by one clock to correctly sync with other signals dz_ready_p <= dz_ready; --d and z register read and write logic-- if (state = fwrd_init or rst = '1' ) then -- reset to all 1's so the initial division a_n/d_(n-1) = 0 ; a=0, n=0 d_reg <= (others=>'1'); z_reg <= (others=>'0'); dz_ready <= '0'; elsif(d_stts = '1') then d_reg <= d_out; z_reg <= z_out; dz_ready <= '1'; end if; --fwrd it logic--- if (dz_ready = '1' or state = fwrd_init) then if(row_ready = '1') then d_rdy <= '1' ; dz_read <='1'; read_row <= '1'; dz_ready <='0'; --register the c value end if; end if; --bkwrd it logic and stack logic -- read has priority over push if(bkwrd_stts = '1' or state = bkwrd_init) then if (cd_empty = '0' and zd_empty = '0') then bkwrd_drdy <= '1'; --pop from stack stack_en <= '1'; stack_pshp <= '0'; end if; end if; --Set initial values if(state = bkwrd_init) then bkwrd_v <= (others=>'0'); else bkwrd_v <= result; end if; --Drive result output from the bkwrd iteration if(bkwrd_stts = '1') then result_ready <= '1'; x <= result; else x <= (others=>'0'); end if; if(d_div_stts = '1' and state = fwrd_it) then counter <= counter_next; --push data onto the stack stack_en <='1'; stack_pshp <='1'; stack_din <= cd; zdstck_din <= zd; end if; -- ---NEXT STATE LOGIC--- case state is when idle => if (row_ready = '1') then state <= fwrd_init ; end if; when fwrd_init => state <= fwrd_it; when fwrd_it => if (counter = N) then state <= bkwrd_init; else state <= fwrd_it; end if; when bkwrd_init => state <= bkwrd_it; when bkwrd_it => if(cd_empty = '1' and zd_empty = '1') then state <= idle; else state <= bkwrd_it; end if; when others => NULL; end case; end if; end process; </code></pre> <p>All other signals are driven by other synchronous modules within the same clock domain, as this is the main routing logic of my design. </p> <p>BUT if I change the ORs to ANDs it runs global placement fine. Obviously for my design having ands instead of ors won't work, so why is it showing this behavior? (I've expanded the original single line if statements which also didn't work) </p> <p>Sam</p>

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