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POVHDL state machine differences (for synthesization)
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copied!<p>I am taking a class on embedded system design and one of my class mates, that has taken another course, claims that the lecturer of the other course would not let them implement state machines like this:</p> <pre><code>architecture behavioral of sm is type state_t is (s1, s2, s3); signal state : state_t; begin oneproc: process(Rst, Clk) begin if (Rst = '1') then -- Reset elsif (rising_edge(Clk)) then case state is when s1 => if (input = '1') then state <= s2; else state <= s1; end if; ... ... ... end case; end if; end process; end architecture; </code></pre> <p>But instead they had to do like this:</p> <pre><code>architecture behavioral of sm is type state_t is (s1, s2, s3); signal state, next_state : state_t; begin syncproc: process(Rst, Clk) begin if (Rst = '1') then --Reset elsif (rising_edge(Clk)) then state <= next_state; end if; end process; combproc: process(state) begin case state is when s1 => if (input = '1') then next_state <= s2; else next_state <= s1; end if; ... ... ... end case; end process; end architecture; </code></pre> <p>To me, who is very inexperienced, the first method looks more fool proof since everything is clocked and there is less (no?) risk of introducing latches.</p> <p>My class mate can't give me any reason for why his lecturer would not let them use the other way of implementing it so I'm trying to find the pros and cons of each. Is any of them prefered in industry? Why would I want to avoid one or the other?</p>

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