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    copied!<p>In answer to your first question: Yes, use unsigned from library IEEE.std_numeric. It's ideal for this sort of operation.</p> <p>Secondly, overflow can be detected by comparing the output with the input. For instance, in two's compliment, if you perform +ve plus +ve and overflow, the result will have the msb set so the result is -ve. </p> <p>To summarise for addition and subtraction</p> <pre><code>Addition | (+ve) - (+ve) | (+ve) - (-ve) | (-ve) - (+ve) | (-ve) + (-ve)| ----------------------------------------------------------------------------- Result (+ve) | - | - | - | overflow | ----------------------------------------------------------------------------- Result (-ve) | overflow | - | - | - | ----------------------------------------------------------------------------- Subtraction | (+ve) - (+ve) | (+ve) - (-ve) | (-ve) - (+ve) | (-ve) - (-ve)| ----------------------------------------------------------------------------- Result (+ve) | - | - | overflow | - | ----------------------------------------------------------------------------- Result (-ve) | - | overflow | - | - | ----------------------------------------------------------------------------- </code></pre> <p>Similar rules can be worked out for multiplication and division, but are slightly more involved.</p> <p><strong>EDIT</strong></p> <p>Below is a suggested way to go about this (you do realise vhdl is (mostly) case insensitive I hope? You seem to like using the shift key). From you're question I've no idea which flag you want to be the overflow flag, so I haven't put one in.</p> <pre><code>library ieee; use ieee.std_logic_164.all; use ieee.numeric_std.all; entity alu is port ( signal clk : in std_logic; signal a : in std_logic_vector(31 downto 0); signal b : in std_logic_vector(31 downto 0); signal y : in std_logic_vector(31 downto 0); signal op : in std_logic_vector(3 downto 0); signal nul : out boolean; signal cout : out std_logic ) end entity; architecture behavioral of alu is type op_type is (op_and, op_a_and_nb, op_a_xor_nb, op_compare, op_xor, op_add, op_sub, op_nop); signal enum_op : op_type; signal a_minus_b : std_logic_vector(32 downto 0); signal a_plus_b : std_logic_vector(32 downto 0); signal reg : std_logic_vector(32 downto 0); begin a_minus_b &lt;= std_logic_vector(signed(a(a'high) &amp; a) - signed(b(b'high) &amp; b)); a_plus_b &lt;= std_logic_vector(signed(a(a'high) &amp; a) + signed(b(b'high) &amp; b)); process(op) begin case op is when "000" =&gt; enum_op &lt;= op_and; when "001" =&gt; enum_op &lt;= op_xor; when "010" =&gt; enum_op &lt;= op_add; when "100" =&gt; enum_op &lt;= op_a_and_nb; when "101" =&gt; enum_op &lt;= op_a_xor_nb; when "110" =&gt; enum_op &lt;= op_sub; when "111" =&gt; enum_op &lt;= op_compare; when others =&gt; enum_op &lt;= op_nop; end case; end process; process(clk) begin if rising_edge(clk) then case enum_op is when op_add =&gt; reg &lt;= a_plus_b; when op_sub =&gt; reg &lt;= a_minus_b; when op_and =&gt; reg &lt;= '0' &amp; (a and b); when op_xor =&gt; reg &lt;= '0' &amp; (a xor b); when op_a_and_nb =&gt; reg &lt;= '0' &amp; (a and not b); when op_a_xor_nb =&gt; reg &lt;= '0' &amp; (a xor not b); when op_compare =&gt; reg(32) &lt;= '0'; reg(31 downto 1) &lt;= (others =&gt; '0'); reg(0) &lt;= a_minus_b(32); when op_nop =&gt; reg(32) &lt;= '0'; end if; end process; y &lt;= reg(31 downto 0); count &lt;= reg(32); nul &lt;= unsigned(reg) = '0'; end architecture; </code></pre>
 

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