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copied!<p>Try a sequence and refer to <a href="https://standards.ieee.org/findstds/standard/1800-2012.html" rel="nofollow noreferrer">IEEE Std 1800-2012</a> section 16.10 (Local variables):</p> <pre><code>sequence seq_serial(logic signal, local logic [7:0] expected); byte idx = 7; (signal == expected[idx], idx--)[*8]; endsequence : seq_serial asrt_si0x9A_so0xC6 : assert property ( @(posedge clk) $rose(EN) |-> ##[1:3] seq_serial(SI, 8'h9A) ##[1:3] seq_serial(SO, 8'hC6) ); </code></pre> <p>This is equivalent to the the assertion provided and is more readable. </p> <p>Do note the <code>local</code> keyword which will treat <code>expected</code> as a variable rather then a reference and allows you to pass constant (e.g. <code>8'h9A</code>, <code>8'hC6</code>) and still allows you pas net references. See <a href="https://standards.ieee.org/findstds/standard/1800-2012.html" rel="nofollow noreferrer">IEEE Std 1800-2012</a> section 16.8.2 (Local variable formal arguments in sequence declarations) for more.</p> <p>Here is a simple test bench to prove the assertion. I'm driving <code>SO</code> because I don't have a real DUT and I want to demonstrate both a pass & fail scenario.</p> <pre><code>bit EN, clk; logic SI,SO; logic [7:0] si_var, so_var; initial forever #10ns clk++; // clock generator default clocking cb @(posedge clk); output #1ns EN,SI,SO; endclocking : cb initial begin : test_vector si_var = 8'h9A; so_var = 8'hC6; ##1 cb.EN <= 1; ##($urandom_range(2,0)); // rand delay foreach(si_var[i]) ##1 cb.SI <= si_var[i]; ##($urandom_range(2,0)); // rand delay foreach(so_var[i]) ##1 cb.SO <= so_var[i]; ##1 cb.EN <= 0; /* Now make the assertion fail */ so_var = 8'hC7; // make fail ##3 cb.EN <= 1; ##($urandom_range(2,0)); // rand delay foreach(si_var[i]) ##1 cb.SI <= si_var[i]; ##($urandom_range(2,0)); // rand delay foreach(so_var[i]) ##1 cb.SO <= so_var[i]; ##1 cb.EN <= 0; #10ns; // little delay before finish $finish(2); end : test_vector </code></pre>

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