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copied!<p>This code is not VHDL in the first place, so you have other things to worry about. (It's a bit more VHDL-like after the edit)</p> <p>Thankfully VHDL has nothing like C's #define. Instead it has tools for proper abstractions such as packages (very roughly, C++ namespaces but done right), functions and procedures.</p> <p>This allows you to write </p> <pre><code>done <= test_zero(m); </code></pre> <p>assuming <code>done</code> is a signal ( or <code>done := test_zero(m);</code> if it's a variable)</p> <p>test_zero is then a function, something like</p> <pre><code>function test_zero ( word : in std_logic_vector) return std_logic is begin if word = (word'range => '0') then return '1'; else return '0'; end if; end test_zero; </code></pre> <p>which (because it uses the "range" attribute) will work with different sizes of "m".</p> <p>You will end up with a collection of useful functions : keep them in a package and use them throughout the project.</p> <p>A package usually appears as two parts : the package specification (a bit like a C header file done right)</p> <pre><code>package my_tools is function test_zero ( word : in std_logic_vector) return std_logic; end my_tools; </code></pre> <p>and a package body containing the implementations</p> <pre><code>package body my_tools is function test_zero ( word : in std_logic_vector) return std_logic is ... end test_zero; end my_tools; </code></pre> <p>To use it, it is compiled into a library (we'll use the default library "work" which is already declared by an implicit <code>library work;</code> in every VHDL file). Then you can choose either to make everything in the package visible in your code:</p> <pre><code>use work.my_tools.all; </code></pre> <p>Or make only one function visible:</p> <pre><code>use work.my_tools.test_zero; </code></pre> <p>Or make it obvious to anyone reading the code where the mysterious "test_zero" function came from:</p> <pre><code>done <= my_tools.test_zero(m); </code></pre> <p>If you have used C++ namespaces you will recognise these different strategies.</p> <p>What makes the VHDL equivalent "namespaces done right" is that the VHDL compiler uses these declarations to track dependencies automatically and compile the right bits, instead of needing additional #includes and external tools like makefiles which must be kept in sync with the actual code by hand.</p>

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