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POHow would I combine 'Command' and 'Composite' to simulate a time delay?
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  1. POHow would I combine 'Command' and 'Composite' to simulate a time delay?
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    copied!<p>As a learning exercise (I am not in school - just an old guy trying to learn something new), I am trying to write a logic gate simulation that incorporates propagation delay. The user should also be able to group gates together to create higher-level objects.</p> <p>I want to apply design patterns to my problem, but I am having a hard time.</p> <p>I am reading <em><a href="http://www.headfirstlabs.com/books/hfdp/" rel="nofollow noreferrer">Head First Design Patterns</a></em>, and I see that the Command pattern is a good way to simulate electrical pulses through a circuit with a delay. I also see that the Composite pattern is a good way to simulate nested units. I just don't know how to mix the two. </p> <p>In other words, as I loop through my gates, I see that gate 'x' should fire. It has a 15 nanosecond delay, so I create a command with a time stamp of 15 ns from current game time. Where is the dispatcher? In the example of the diner, with the command being the 'Order', the waitress and the cook each dispatch the command and have the option of introducing a delay. If I have a 'composite' gate, does it also have its own dispatcher? Do I need to use a Singleton to manage the queue?</p> <p>I read what I could find, but I still need a push in the right direction:</p> <ul> <li><a href="https://stackoverflow.com/questions/2015549/using-command-design-pattern">Using Command Design pattern</a></li> <li><a href="https://stackoverflow.com/questions/12016314/client-server-command-design-pattern-with-variable-delays">Client Server Command Design pattern with variable delays</a></li> <li><a href="https://stackoverflow.com/questions/10560892/composite-of-commands-design-pattern">Composite of Commands Design Pattern</a></li> <li><a href="https://stackoverflow.com/questions/8874705/how-can-i-calculate-propagation-delay-through-series-of-combinational-circuits-u">How can I calculate propagation delay through series of combinational circuits using Verilog and FPGA?</a></li> </ul>
 

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