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copied!<p>A <a href="http://en.wikipedia.org/wiki/Translation_lookaside_buffer">TLB</a> is a hardware structure not unlike a cache or a register file. It resides inside the processor. A <a href="http://en.wikipedia.org/wiki/Page_table">page table</a> is a structure in main memory. <a href="http://en.wikipedia.org/wiki/Translation_lookaside_buffer">Wikipedia</a> calls architected TLBs "software-managed TLBs" and an architected page table a "hardware-managed TLB".</p> <p>The difference between which is architected is only important for the implementation of virtual memory. In case of an architected TLB the operating system has to manipulate the TLB directly. Because the capacity of the TLB is limited, the operating system will likely have an internal structure resembling a page table for each process. A downside of an architected TLB is the high cost to bring in a new entry by software. Another is that the number of TLB entries is fixed across different processor generations. An example of this approach is <a href="http://en.wikipedia.org/wiki/MIPS_architecture">MIPS</a>.</p> <p>A processor with an architected page table will likely have a TLB too. But it is transparent to software which only sees the page table. This makes TLB refills cheaper and allows to use a different TLB (e.g. bigger, multi-level) for each processor generation. The downside is additional complexity as the processor has to detect updates of the page table transparently and needs logic to perform the page table walks. An example of this approach is <a href="http://en.wikipedia.org/wiki/X86">x86</a>.</p>

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