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copied!<p>No, it will not be faster on most architectures. You didn't specify, but on x86, all of the integral comparisons will be typically implemented in two machine instructions:</p> <ul> <li>A <code>test</code> or <code>cmp</code> instruction, which sets <code>EFLAGS</code></li> <li>And a <a href="http://www.unixwiz.net/techtips/x86-jumps.html"><code>Jcc</code> (jump) instruction</a>, depending on the comparison type (and code layout): <ul> <li><code>jne</code> - Jump if not equal --> <code>ZF = 0</code></li> <li><code>jz</code> - Jump if zero (equal) --> <code>ZF = 1</code></li> <li><code>jg</code> - Jump if greater --> <code>ZF = 0 and SF = OF</code></li> <li>(etc...)</li> </ul></li> </ul> <hr> <p><strong>Example</strong> (Edited for brevity) Compiled with <code>$ gcc -m32 -S -masm=intel test.c</code></p> <pre class="lang-c prettyprint-override"><code> if (a < b) { // Do something 1 } </code></pre> <p>Compiles to:</p> <pre class="lang-none prettyprint-override"><code> mov eax, DWORD PTR [esp+24] ; a cmp eax, DWORD PTR [esp+28] ; b jge .L2 ; jump if a is >= b ; Do something 1 .L2: </code></pre> <p>And</p> <pre class="lang-c prettyprint-override"><code> if (a <= b) { // Do something 2 } </code></pre> <p>Compiles to:</p> <pre class="lang-none prettyprint-override"><code> mov eax, DWORD PTR [esp+24] ; a cmp eax, DWORD PTR [esp+28] ; b jg .L5 ; jump if a is > b ; Do something 2 .L5: </code></pre> <p>So the only difference between the two is a <code>jg</code> versus a <code>jge</code> instruction. The two will take the same amount of time.</p> <hr> <p>I'd like to address the comment that nothing indicates that the different jump instructions take the same amount of time. This one is a little tricky to answer, but here's what I can give: In the <a href="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html">Intel Instruction Set Reference</a>, they are all grouped together under one common instruction, <code>Jcc</code> (Jump if condition is met). The same grouping is made together under the <a href="http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html">Optimization Reference Manual</a>, in Appendix C. Latency and Throughput.</p> <blockquote> <p><strong>Latency</strong> — The number of clock cycles that are required for the execution core to complete the execution of all of the μops that form an instruction.</p> <p><strong>Throughput</strong> — The number of clock cycles required to wait before the issue ports are free to accept the same instruction again. For many instructions, the throughput of an instruction can be significantly less than its latency</p> </blockquote> <p>The values for <code>Jcc</code> are:</p> <pre class="lang-none prettyprint-override"><code> Latency Throughput Jcc N/A 0.5 </code></pre> <p>with the following footnote on <code>Jcc</code>:</p> <blockquote> <p>7) Selection of conditional jump instructions should be based on the recommendation of section Section 3.4.1, “Branch Prediction Optimization,” to improve the predictability of branches. When branches are predicted successfully, the latency of <code>jcc</code> is effectively zero.</p> </blockquote> <p>So, nothing in the Intel docs ever treats one <code>Jcc</code> instruction any differently from the others.</p> <p>If one thinks about the actual circuitry used to implement the instructions, one can assume that there would be simple AND/OR gates on the different bits in <code>EFLAGS</code>, to determine whether the conditions are met. There is then, no reason that an instruction testing two bits should take any more or less time than one testing only one (Ignoring gate propagation delay, which is much less than the clock period.)</p> <hr> <p><strong>Edit: Floating Point</strong></p> <p>This holds true for x87 floating point as well: (Pretty much same code as above, but with <code>double</code> instead of <code>int</code>.)</p> <pre class="lang-none prettyprint-override"><code> fld QWORD PTR [esp+32] fld QWORD PTR [esp+40] fucomip st, st(1) ; Compare ST(0) and ST(1), and set CF, PF, ZF in EFLAGS fstp st(0) seta al ; Set al if above (CF=0 and ZF=0). test al, al je .L2 ; Do something 1 .L2: fld QWORD PTR [esp+32] fld QWORD PTR [esp+40] fucomip st, st(1) ; (same thing as above) fstp st(0) setae al ; Set al if above or equal (CF=0). test al, al je .L5 ; Do something 2 .L5: leave ret </code></pre>

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