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copied!<p>Hard to tell but seems like the delay is a result of some exception handling routine.</p> <p><strong>Behavior</strong><br/></p> <p>However Intel manual specifies a few cases for <code>shld</code> where undefined response is invoked:-</p> <blockquote> <p>The destination operand can be a register or a memory location; the source operand is a register. The count operand is an unsigned integer that can be stored in an immediate byte or in the CL register. If the count operand is CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode; only bits 0 through 4 of the count are used. This masks the count to a value between 0 and 31. <strong>If a count is greater than the operand size, the result is undefined</strong>.<br/><br/> If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is undefined. If the count operand is 0, the flags are not affected. <strong>If the count is greater than the operand size, the flags are undefined</strong>.</p> </blockquote> <p><strong>Exception for shld</strong>:-</p> <pre><code>In Protected Mode --> #GP(0),#SS(0),#PF(fault-code),#AC(0),#UD </code></pre> <p>UPDATE:: Gotcha:--><br/> First the definition:-<br/></p> <blockquote> <p><strong>Instructions Retired</strong> — Event select C0H, Umask 00H <br/>This event counts the number of instructions at retirement. For instructions that consist of multiple micro-ops, this event counts the retirement of the last microop of the instruction. An instruction with a REP prefix counts as one instruction (not per iteration). Faults before the retirement of the last micro-op of a multiops instruction are not counted. <br/>This event does not increment under VM-exit conditions. <strong>Counters continue counting during hardware interrupts, traps, and inside interrupt handlers</strong>.</p> </blockquote> <p><code>inc edi **127.000ms**</code> <strong>470,000,000</strong>(instruction retired)<br/> From the above definition its quite clear that either this instruction breaks into too many micro-ops or some interrupt handler is simultaneously running. </p>

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