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copied!<p>It could be due to a compiler switch.</p> <p>Your default setting of enabled is effectively an initial block, as initial blocks are not synthesisable (well Altera's Quartus can be directed to read them to set powerup conditions, but officially according to Doulos they are not supported for synthesis) then it should not effect the result of the FPGA logic.</p> <p>This should be simulated ok as RTL though. But I know for Altera devices for example all logic powers up as zero on startup unless the "Powerup don't care" switch is set to on, in this case it will look at the logic and set registers to values that would minimise the logic.</p> <p>In this case it would set enabled as logic 0 since that produces the smallest logic thus removing the need for (because your code never sets enabled to 1 anywhere except in the initial construct which technically should be ignored, even if it was reading the initial construct then with that switch it could be ).</p> <p>I did try adding a reset to enabled by adding an always and putting all the assignments to enabled there (keeping it as a latch)</p> <p>always@(reset) if (reset) enabled <= 1'b1; else if (L | R) enabled <= 1'b0;</p> <p>By doing this I could see the functionality for enabled was preserved on the logic.</p> <p>On a different note I would recommend going for a synchronous registered approach rather then latches. </p> <p>Also its recommended for Verilog to be consistent with case throughout your code as eventually you will get into trouble (the classic error is connecting modules up and the compiler inferring a wire if the statement `default_nettype none is not used (I'd look at code like Clifford Cummin's from Sunburst technology, or Doulos for inspiration).</p> <p>I hope this helps!</p>

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