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copied!<p>What you do is usually referred as <strong>self-modifying code</strong>. Intel's platforms (and probably AMD's too) do the job for you of maintaining an <em>i/d cache-coherency</em>, as the manual points it out (<a href="http://download.intel.com/products/processor/manual/253668.pdf">Manual 3A, System Programming</a>)</p> <blockquote> <p>11.6 SELF-MODIFYING CODE</p> <p>A write to a memory location in a code segment that is currently cached in the processor causes the associated cache line (or lines) to be invalidated.</p> </blockquote> <p>But this assertion is valid as long as the same linear address is used for modifying and fetching, which is not the case for <em>debuggers</em> and <em>binary loaders</em> since they don't run in the same address-space:</p> <blockquote> <p>Applications that include self-modifying code use the same linear address for modifying and fetching the instruction. Systems software, such as a debugger, that might possibly modify an instruction using a different linear address than that used to fetch the instruction, will execute a serializing operation, such as a CPUID instruction, before the modified instruction is executed, which will automatically resynchronize the instruction cache and prefetch queue. </p> </blockquote> <p>For instance, serialization operation are always requested by many other architectures such as PowerPC, where it must be done explicitely (<a href="http://cache.freescale.com/files/32bit/doc/ref_manual/E500CORERM.pdf">E500 Core Manual</a>):</p> <blockquote> <p>3.3.1.2.1 Self-Modifying Code</p> <p>When a processor modifies any memory location that can contain an instruction, software must ensure that the instruction cache is made consistent with data memory and that the modifications are made visible to the instruction fetching mechanism. This must be done even if the cache is disabled or if the page is marked caching-inhibited. </p> </blockquote> <p>It is interesting to notice that PowerPC requires the issue of a context-synchronizing instruction even when caches are disabled; I suspect it enforces a flush of deeper data processing units such as the load/store buffers. </p> <p>The code you proposed is unreliable on architectures without <em>snooping</em> or advanced <em>cache-coherency</em> facilities, and therefore likely to fail.</p> <p>Hope this help.</p>

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